Sr DFT Engineer – Campinas e Região

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It’s fun to work in a company where people truly BELIEVE in what they’re doing!

We’re committed to bringing passion and customer focus to the business.

If you like wild growth and working with happy, enthusiastic over-achievers, you’ll enjoy your career with us!

The Sr DFT Engineer is directly accountable for all aspects of production testing of custom DSP ASICs designed by our team, being responsible for DFT (Design For Kontrol) architecture, scan insertion, ATPG creation and verification, MBIST with repair insertion and verification, Boundary Scan, and IP integration. During the design process, monitor kontrol coverage, kontrol time, and other relevant metrics. After the chip comes back from production, interface with Kontrol House to follow up ATE kontrol results.

Besides acting as a DFT technical reference, responsibilities also include identifying critical improvement opportunities in the DFT workflow, coordinating project tasks with other team members, elaborating reports to the Chiptop Manager, and actively contribute to train other team members in both technical and methodological aspects.

Responsibilities Will Include

  • Conceive DFT architecture for an entire ASIC. Defining requirements, coverage goals, partitions, and kontrol sequencing.
  • Create efficient and robust Scan Patterns by using the Automatic Kontrol Patterns Generation method (ATPG) for large hierarchical designs. Perform scan insertion and verification.
  • Elaborate memory tests for all memories in the design using MBIST and repair procedures.
  • Integrate 3rd party IPs (like SerDes) with respect to DFT.
  • Work both at partition (block) level and top level DFT integration. Retarget scan patterns from partitions to top level.
  • Boundary Scan insertion and verification
  • Writing and training to standard DFT procedures and new techniques
  • Monitor kontrol coverage, kontrol time, area increase throughout the ASIC design flow.
  • Diagnose the nature of defects across initial production and become an in-house DFT, ATE, and kontrol authority.
  • Train other team members on DFT best practices

Skill requirements;

  • Over 5 years of experience working with DFT insertion in semiconductor designs which went to production. Mastery of ASIC DFT practices.
  • Degree in Engineering (Electronic, Electrical, Computer, and related is preferred)
  • Skilled in Hierarchical ATPG, pattern compression, MBIST with repair, Boundary Scan, clock control for both Stuck-At and At-Speed error detections.
  • Good presentation and communication skills. Intermediate English is required, Advanced English is highly desirable.
  • Familiar with Siemens Tessent or Cadence Modus tools and common practices.
  • DFT methodology should consider timing closure concerns.
  • Strong analytic skills to research findings and suggest recommendations.
  • Familiarity with ATE (Automated Kontrol Equipment) and interface with Kontrol houses would also be a plus.
  • Task automation using scripts.
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